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19
FN6808.3
October 1, 2009
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 25.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 26 through 28. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 26 and 27.
This dual transformer scheme is used to improve common-
mode rejection, which keeps the common-mode level of the
input matched to VCM. The value of the shunt resistor
should be determined based on the desired load impedance.
The differential input resistance of the KAD5512HP is 500
Ω.
The SHA design uses a switched capacitor input stage (see
Figure 41), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes
a disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier, as shown in Figure 28, can be used in
applications that require DC-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 42).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 29. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC-coupling.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
FIGURE 25. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.535V
0.725V
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADT1-1WT
0.1F
KAD5512HP
VCM
ADT1-1WT
1000pF
FIGURE 27. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
ADTL1-12
0.1F
KAD5512HP
VCM
ADTL1-12
1000pF
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
KAD5512HP
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Ω
FIGURE 29. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
AVDD
200O
200pF
CLKP
CLKN
1kO
1000pF
Ω
KAD5512HP
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